The present invention relates to a programmable semiconductor memory apparatus (called an RWM: Read/Write Memory) and more particularly to an RWM with a circuit for storing a device identifying code.
An RWM can be generally divided into a RAM (Random Access Memory) and a ROM (Read Only Memory). A programmable ROM corresponds to an RWM. A programmable ROM is classified from the viewpoint of structure into a bipolar-type, a FAMOS (Floating-gate Avalanche Injection MOS) or an MNOS (Metal Nitride Oxide Semiconductor), and classified from the viewpoint of whether it is applied into a fuse ROM (programmable ROM), an EP-ROM(Erasable Programmable ROM), an EEP-ROM (Electrically Erasable and Programmable ROM), or an EA-ROM (Electrically Alterable ROM).
An RWM is forwarded from the manufacturer in a blank state, i.e., in a state where the data is not written, the user-side writes data by ROM writer. A ROM writer has a function of automatically setting a condition for writing data into an RWM device. Therefore, a circuit for storing a self device identifying code and enabling the self device identifying code to be read upon writing data into RWM is generally provided on the device side. The self device identifying code represents the conditions for writing data into an RWM such as the name of a manufacturer memory capacity, the kind of writing algorithm and chip revision of the RWM.
FIG. 1 shows the structure of a prior art RWM circuit for explaining the operation of the RWM.
An RWM generally comprises a first memory cell array 1 to a k-th memory cell array 3, and data sense circuits 4. More precisely, a RWM comprises bit lines B.sub.1 to B.sub.m, word lines W.sub.1 to W.sub.n and W.sub.c, memory transistors Q.sub.11 to Q.sub.mn, bit line selection transistors Q.sub.1s to Q.sub.ms, device identifying code storing transistors Q.sub.1c to Q.sub.kc and bus lines B.sub.u1 to B.sub.uk.
When a memory write is performed in the RWM, an address signal is produced to select one word line (for example W.sub.1) and one bit line (for example B.sub.1) to select a predetermined memory transistor Q.sub.11, and data is written by applying an "H" signal or an "L" signal to memory transistor circuit Q.sub.11. When data is read, a predetermined memory transistor Q.sub.11 is selected by the same operation as above, thereby outputting the stored data. Generally, the device identifying code is stored in device identifying code storing transistors Q.sub.1c to Q.sub.kc connected to the bit line. In the prior art shown in FIG. 1, a device identifying code storing transistors Q.sub.1c to Q.sub.kc is provided for respective memory cell arrays and as k device identifying code storing transistors Q.sub.1c to Q.sub.kc are used, the number of device identifying codes comprises k bits. In a device of this type, only the exclusive word line W.sub.c may be selected to enable the device identifying code to be read out. This makes a device of this type easy to pattern and thus it is widely used.
In accordance with a recent increase in the degree of LSI integration, a redundant bit line is generally provided to increase yield. A redundant bit line is provided by preparing several spare bit lines in the memory. Thus, even if a faulty bit line, word line or memory cell exists in a memory, a spare bit line is selected when an address signal selecting the faulty portion enters the memory. Thus, a device containing a fault can be used as if it were fault-free. When a redundant bit line is embodied, there is always a possibility of replacing a discretional bit line by a spare bit line. In this case the replaced bit line is not used thereafter. When the device identifying code storing transistor Q.sub.ic is connected to the replaced bit line, an element of the device identifying code stored in the device identifying code storing transistor Q.sub.ic, for example, the i-th element of the k-bit code, is lacking and thus cannot be read out. This prevents the device identifying code from performing an effective function. Therefore, when the bit line redundancy is embodied, the type with the device identifying code stored in the device identifying code storing transistor connected to the bit line cannot be used.